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- 1 - rev.0.2, may. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. K9F4G08U0D k9k8g08u0d k9k8g08u1d k9wag08u1d advance 4gb d-die nand flash single-level-cell (1bit/cell) datasheet www..net
- 2 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d revision history the attached data sheets are prepared and approved by samsung el ectronics. samsung electronics co ., ltd. reserve the right to c hange the specifications. samsung electr onics will evaluate and reply to your requests and questions ab out device. if you have any questi ons, please contact the samsung branch office near your office. revision no. history draft date remark editor 0.0 1. initial issue jan. 12, 2010 advance - 0.1 1. corrected errata. 2. chapter 1.2 features revised. may. 03, 2010 advance h.k.kim 0.2 1. ddp/qdp part id are added. may. 26, 2010 advance h.k.kim www..net
- 3 - table of contents datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 1.0 introduction ........... .............. .............. .............. .............. ............ ........... ........... .......... ......................................... 4 1.1 general description........................................................................................................ ......................................... 4 1.2 features ................................................................................................................... ............................................... 4 1.3 product list ............................................................................................................... ....................................... 4 1.4 pin configuration (tsop1).................................................................................................. .................................... 5 1.4.1 package dimensions ....................................................................................................... .......................... 5 1.5 pin configuration (tsop1).................................................................................................. .................................... 6 1.5.1 package dimensions ....................................................................................................... .......................... 6 1.6 pin description ............................................................................................................ ............................................ 7 2.0 product introduction....................................................................................................... ............................... 9 2.1 absolute maximum ratings ...... ............................................................................................. .................................. 10 2.2 recommended operating conditions ..................... ...................................................................... .......................... 10 2.3 dc and operating characteristics(recomme nded operating conditions otherwise noted.) ..................10 2.4 valid block................................................................................................................ ............................................... 11 2.5 ac test condition .......................................................................................................... .......................................... 11 2.6 capacitance(ta=25c, vcc=3.3v, f=1.0mhz) ................................................................................... .................... 11 2.7 mode selection............................................................................................................. ........................................... 11 2.8 program / erase characteristics ............................................................... .........................................................12 2.9 ac timing characteristics for command / address / da ta input ............................................................... ............. 12 2.10 ac characteristics for operation................... ....................................................................... ................................. 13 3.0 nand flash technical notes ... ............................................................................................. .................................... 14 3.1 initial invalid block(s) ................................................................................................... ............................................ 14 3.2 identifying initial invalid blo ck(s) ....................................................................................... ...................................... 14 3.3 error in write or read operation........................................................................................... ..................................... 15 3.4 addressing for program operation ................... ........................................................................ ................................ 17 3.5 system interface using ce don?t-care. ...................................................................................... ............................. 18 4.0 timing diagrams ........................................................................................................... ....................................... 19 4.1 command latch cycle ....................................................................................................... .................................... 19 4.2 address latch cycle....................................................................................................... ........................................ 19 4.3 input data latch cycle .................................................................................................... ....................................... 20 4.4 * serial access cycle after read(cle=l, we=h, al e=l)...................................................................... ............... 20 4.5 serial access cycle after read(edo type, cle=l, we=h, ale=l) .............................................................. ...... 21 4.6 status read cycle ......................................................................................................... ......................................... 21 4.7 read operation ............................................................................................................ .......................................... 22 4.8 read operation(intercepted by ce) ......................................................................................... .............................. 22 4.9 random data output in a page .............................................................................................. ............................... 23 4.10 page program operation................................................................................................... ................................... 24 4.11 page program operation with ra ndom data input ............ .............. .............. .............. ........... ........... .................. 25 4.12 copy-back program operation ......................... ..................................................................... .............................. 26 4.13 copy-back program operation with random data in put ....................................................................... .............. 27 4.14 two-plane page program operat ion .............. .............. .............. .............. ........... ........... ........... .......................... 28 4.15 block erase operation.................................................................................................... ...................................... 29 4.16 two-plane block erase operatio n ............... .............. .............. .............. ........... ........... ........... ............................. 30 4.17 read id operation........................................................................................................ ........................................ 31 5.0 device operation ........................................................................................................... ..................................... 33 5.1 page read.................................................................................................................. ............................................. 33 5.2 page program ............................................................................................................... .......................................... 34 5.3 copy-back program.......................................................................................................... ....................................... 35 5.4 block erase ................................................................................................................ ............................................. 36 5.5 two-plane page program..................................................................................................... ................................... 36 5.6 two-plane block erase...................................................................................................... ...................................... 37 5.7 two-plane copy-back program................................................................................................ ............................... 37 5.8 read status................................................................................................................ ............................................. 39 5.9 read id .................................................................................................................... ............................................... 40 5.10 reset ..................................................................................................................... ................................................ 40 5.11 ready/busy ................................................................................................................ ........................................... 41 5.12 data protection & power up seque nce ............. .............. .............. .............. ............ ........... ......... ......................... 42 www..net
- 4 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 1.0 introduction 1.1 general description offered in 512mx8bit, the K9F4G08U0D is a 4g-bit nand flash memory with spare 128m-bit. the device is offered in 3.3v vcc. its nand cell provides the most cost-effective solution for the solid state applicati on market. a program operation can be performed in typical 250 s on the (2k+64)byte page and an erase operation can be performed in typical 2ms on a (128k+4k) byte block. data in the data register can be read out at 2 5ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. the on-chip write controller automa tes all program and erase functions including pulse repetition, wher e required, and internal verification and ma rgining of data. even the write-intensive systems can take advantage of the K9F4G08U0D s extended reliability of 100k program/erase cycles by providing ecc(error correcting code) with real time mapping-out algorith m. the K9F4G08U0D is an optimum solution for large nonvolatile stor age applications such as solid state file storage and other por table applications requir- ing non-volatility. 1.2 features 1.3 product list ? voltage supply - 3.3v device(K9F4G08U0D) : 2.7v ~ 3.6v ? organization - memory cell array : (512m + 16m) x 8bit - data register : (2k + 64) x 8bit ? automatic program and erase - page program : (2k + 64)byte - block erase : (128k + 4k)byte ? page read operation - page size : (2k + 64)byte - random read : 25 s(max.) - serial access : 25ns(min.) ? fast write cycle time - page program time : 250 s(typ.) - block erase time : 2ms(typ.) ? command/address/data multiplexed i/o port ? hardware data protection - program/erase lockout during power transitions ? reliable cmos floating-gate technology - ecc requirement : 1bit/528byte - endurance & data retention : please refer to the qualification report ? command register operation ? unique id for copyright protection ? package : - K9F4G08U0D-scb0/sib0 : pb-free, halogen-free package 48 - pin tsop1 (12 x 20 / 0.5 mm pitch) - k9k8g08u0d-scb0/sib0 : pb-free, halogen-free package 48 - pin tsop1 (12 x 20 / 0.5 mm pitch) - k9k8g08u1d-scb0/sib0 : pb-free, halogen-free package 48 - pin tsop1 (12 x 20 / 0.5 mm pitch) - k9wag08u1d-scb0/sib0 : pb-free, halogen-free package 48 - pin tsop1 (12 x 20 / 0.5 mm pitch) part number vcc range organization pkg type K9F4G08U0D-s 2.70 ~ 3.60v x8 tsop1 k9k8g08u0d-s k9k8g08u1d-s k9wag08u1d-s www..net
- 5 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 1.4 pin configuration (tsop1) 1.4.1 package dimensions K9F4G08U0D-scb0/sib0 k9k8g08u0d-scb0/sib0 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c r/b 1 re ce1 n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c n.c 48-pin lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () www..net
- 6 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 1.5 pin configuration (tsop1) 1.5.1 package dimensions 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c r/b 1 re ce1 ce2 n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c k9wag08u1d-scb0/sib0 r/b 2 k9k8g08u1d-scb0/sib0 48-pin lead free plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 0.010 0.25 typ 0.125 +0.075 0.035 0.005 +0.003 -0.001 0.50 0.020 () www..net
- 7 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 1.6 pin description note : connect all vcc and vss pins of each de vice to common power supply outputs. do not leave vcc or vss disconnected. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands s ent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the acti vating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase operation. re read enable the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the fall- ing edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent program/erase protection duri ng power transitions. the internal high voltage generator is reset when the wp pin is active low. r/b ready/busy output the r/b output indicates the status of the device operation. when lo w, it indicates that a program, erase or random read oper- ation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z conditio n when the chip is deselected or when outputs are disabled. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. www..net
[figure 2] K9F4G08U0D array organization [figure 1] K9F4G08U0D functional block diagram - 8 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d note : column address : starting address of the register. * l must be set to "low". * the device ignores any additional input of address cycles than required. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 8 a 9 a 10 a 11 *l *l *l *l 3rd cycle a 12 a 13 a 14 a 15 a 16 a 17 a 18 a 19 4th cycle a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 5th cycle a 28 a 29 *l *l *l *l *l *l v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 12 - a 29 a 0 - a 11 command ce re we cle wp i/0 0 i/0 7 v cc v ss ale 4,096m + 128m bit nand flash array (2,048 + 64)byte x 262,144 y-gating data register & s/a 2k bytes 64 bytes 256k pages (=4,096 blocks) 2k bytes 8 bit 64 bytes 1 block = 64 pages (128k + 4k) byte i/o 0 ~ i/o 7 1 page = (2k + 64)bytes 1 block = (2k + 64)b x 64 pages = (128k + 4k) bytes 1 device = (2k+64)b x 64pages x 4,096 blocks = 4,224 mbits page register column address row address : page address : a 12 ~ a 17 plane address : a 18 block address : a 19 ~ the last address www..net
- 9 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 2.0 product introduction the K9F4G08U0D is a 4,224mbit(4,429,185,024 bit) memory organized as 262,144 rows(pages) by 2,112x8 columns. spare 64x8 columns are located from column address of 2,048~2,111. a 2,112-byte data register is connected to memory cell arrays accommodating data transfer b etween the i/o buffers and memory during page read and page program operations. the memory ar ray is made up of 32 cells that are serially connected to form a nand struc- ture. each of the 32 cells resides in a different page. a block consists of two nand structur ed strings. a nand structure consi sts of 32 cells. total 1,081,344 nand cells reside in a block. the program and read oper ations are executed on a page basis, while the erase operation is executed on a block basis. the memory array consists of 4,096 separately erasable 128k-byte blocks. it indicates t hat the bit by bit erase operatio n is prohibited on the K9F4G08U0D. the K9F4G08U0D has addresses multiplexed into 8 i/os. this sc heme dramatically reduces pin c ounts and allows system upgrades to future densities by maintaining consistency in system board design. command, address and data are all writt en through i/o's by bringing we to low while ce is low. those are latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. some comm ands require one bus cycle. for example, reset command, status read command, etc requi re just one cycle bus. some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the othe r cycle for execution. the 528m byte physical space requires 30 a ddresses, thereby requiring fi ve cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that order. page read and page program need the same five addr ess cycles following the required command input. in block eras e operation, however, only the three row address cycles are used. device operations are selected by writin g specific commands into the command regist er. table 1 defines the specific commands of the K9F4G08U0D. in addition to the enhanced architecture and interface, the devic e incorporates copy-back program feature from one page to anot her page without need for transporting the data to and from the external buffer memory. since the time-consuming serial access and data-input cycles are removed, system per- formance for solid-state disk appl ication is signifi cantly increased. [table 1] command sets note : 1) random data input/output can be executed in a page. 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st cycle 2nd cycle acceptable command during busy read 00h 30h read for copy back 00h 35h read id 90h - reset ffh - o page program 80h 10h two-plane page program (2) 80h---11h 81h---10h copy-back program 85h 10h two-plane copy-back program (2) 85h---11h 81h---10h block erase 60h d0h two-plane block erase 60h---60h d0h random data input (1) 85h - random data output (1) 05h e0h read status 70h o read status 2 f1h o www..net
- 10 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 2.1 absolute maximum ratings note : 1) minimum dc voltage is -0.6v on input/output pins. during tran sitions, this level may undershoo t to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data shee t. exposure to absolute maximum ra ting conditions for extended per iods may affect reliability. 2.2 recommended operating conditions (voltage reference to gnd, k9xxg08xxd-xcb0 : t a =0 to 70 c, k9xxg08xxd-xib0 : t a =-40 to 85 c) 2.3 dc and operating characteristics(recommended operating conditions otherwise noted.) note : 1) vil can undershoot to -0.4v and vih can overshoot to vcc + 0.4v for durations of 20 ns or less. 2) typical value is measured at vcc=/3.3v, ta=25 c. not 100% tested. 3) the typical value of the k9k8g08u1d's isb2 is 20 a and the maximum value is 100 a. 4) the typical value of the k9k8g08u0d's isb2 is 20 a and the maximum value is 100 a. 5) the typical value of the k9wag08u1d's isb2 is 40 a and the maximum value is 200 a. parameter symbol rating unit voltage on any pin relative to vss v cc -0.6 to +4.6 v v in -0.6 to +4.6 v i/o -0.6 to vcc + 0.3 (< 4.6v) temperature under bias k9xxg08xxd-xcb0 t bias -10 to +125 c k9xxg08xxd-xib0 -40 to +125 storage temperature k9xxg08xxd-xcb0 t stg -65 to +150 c k9xxg08xxd-xib0 short circuit current i os 5ma parameter symbol K9F4G08U0D(3.3v) unit min typ. max supply voltage v cc 2.7 3.3 3.6 v supply voltage v ss 000 v parameter symbol test conditions 3.3v min typ max unit operating current page read with serial access i cc 1 trc=50ns, ce =v il i out =0ma -1530 ma program i cc 2- -1530 erase i cc 3- -1530 stand-by current(ttl) i sb 1ce =v ih , wp =pre =0v/v cc --1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =pre =0v/v cc -1050 a input leakage current i li v in =0 to vcc(max) - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 input high voltage v ih* -2.0- v cc +0.3 v input low voltage, all inputs v il* --0.3-0.8 output high voltage level v oh K9F4G08U0D :i oh =-400 a2.4-- output low voltage level v ol K9F4G08U0D :i ol =2.1ma - - 0.4 output low current(r/b )i ol (r/b ) K9F4G08U0D :v ol =0.4v 8 10 - ma www..net
- 11 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 2.4 valid block note : 1) the device may include initial invalid blocks when first ship ped. additional invalid blocks may develop while being used. th e number of valid blocks is presented with both cases of invalid blocks considered . invalid blocks are defined as bl ocks that contain one or more bad bits. do not erase or pro gram factory-marked b ad blocks. refer to the attached technical notes for appropriate management of invalid blocks. 2) the 1st block, which is placed on 00h block address, is guar anteed to be a valid block up to 1k program/erase cycles with 1 bit/528byte ecc. 3) the number of valid block is on the basis of single pla ne operations, and this may be decreased with two plane operations. 2.5 ac test condition (k9xxg08uxd-xcb0 :t a =0 to 70 c, k9f4g08uxd-xib0:t a =-40 to 85 c, k9xxg08uxd: vcc=2.7v~3.6v unless otherwise noted) 2.6 capacitance ( t a =25 c, v cc =3.3v, f=1.0mhz) note : 1) capacitance is periodically sampled and not 100% tested. 2) c i/o(w)* and c in(w)* are tested at wafer level. 2.7 mode selection note : 1) x can be v il or v ih. 2) wp should be biased to cmos high or cmos low for standby. parameter symbol min typ. max unit K9F4G08U0D n vb 4,016 - 4,096 blocks k9k8g08u0d 8,032 8,192 k9k8g08u1d k9wag08u1d 16,064 16,384 parameter k9xxg08uxd input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load 1 ttl gate and cl=50pf item symbol test condition min max unit input/output capacitance c i/o v il =0v - 8 pf c i/o(w)* v il =0v - 5 pf input capacitance c in v in =0v - 8 pf c in(w)* v in =0v - 5 pf cle ale ce we re wp mode hll hx read mode command input l h l h x address input(5clock) hll hh write mode command input l h l h h address input(5clock) lll hh data input l l l h x data output x x x x h x during read(busy) x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect xxhxx 0v/v cc (2) stand-by www..net
- 12 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 2.8 program / erase characteristics note : 1) typical value is measured at vcc=3.3v, t a =25 c. not 100% tested. 2) typical program time is defined as the time within which mo re than 50% of the whole pages are programmed at 3.3v vcc and 25 c temperature . 2.9 ac timing characteristics for command / address / data input note : 1) the transition of the corresponding c ontrol pins must occur only once while we is held low 2) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle parameter symbol min typ max unit program time t prog - 250 750 s dummy busy time for two-plane page program t dbsy -0.51 s number of partial program cycles nop - - 4 cycles block erase time t bers -2.010ms parameter symbol min max unit cle setup time t cls (1) 12 - ns cle hold time t clh 5-ns ce setup time t cs (1) 20 - ns ce hold time t ch 5-ns we pulse width t wp 12 - ns ale setup time t als (1) 12 - ns ale hold time t alh 5- ns data setup time t ds (1) 12 - ns data hold time t dh 5-ns write cycle time t wc 25 - ns we high hold time t wh 10 - ns address to data loading time t adl (2) 70 - ns www..net
- 13 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 2.10 ac characteristics for operation note : 1) if reset command(ffh) is written at ready state, the device goes into busy for maximum 5 s. parameter symbol min max unit data transfer from cell to register t r -25 s ale to re delay t ar 10 - ns cle to re delay t clr 10 - ns ready to re low t rr 20 - ns re pulse width t rp 12 - ns we high to busy t wb -100 ns read cycle time t rc 25 - ns re access time t rea -20ns ce access time t cea -25ns re high to output hi-z t rhz - 100 ns ce high to output hi-z t chz -30ns re high to output hold t rhoh 15 - ns re low to output hold t rloh 5- ns ce high to output hold t coh 15 - ns re high hold time t reh 10 - ns output hi-z to re low t ir 0-ns re high to we low t rhw 100 - ns we high to re low t whr 60 - ns device resetting time(read/program/erase) t rst - 5/10/500 (1) s www..net
- 14 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 3.0 nand flash technical notes 3.1 initial invalid block(s) [figure 3] flow chart to create initial invalid block table initial invalid blocks are defined as blocks that contain one or mor e initial invalid bits whose reliability is not guaranteed by samsung. the information regarding the initial invalid block(s) is called the initial inva lid block information. devices with initial invalid block(s) h ave the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a sele ct transistor. the system design must be able to mask out the initial invalid block(s) via address mapping. the 1st block, which is placed on 00h block addr ess, is guaranteed to be a valid block up to 1k program/erase cycles with 1bit /528byte ecc. 3.2 identifying initial invalid block(s) all device locations are erased(ffh) except locations where the in itial invalid block(s) informat ion is written prior to shipping. the initial invalid block(s) status is defined by the 1st byte in the spare area. samsung make s sure that either the 1st or 2nd page of every initial invali d block has non-ffh data at the column address of 2048. since the initial invalid block info rmation is also erasable in most cases, it is impossible to recover the information once it has been erased. therefore, the system must be able to recognize the initial invalid block(s) bas ed on the original initial invalid block information and cre- ate the initial invalid block table via the following suggested flow char t(figure 3). any intentional erasure of the original i nitial invalid block information is prohibited. * check "ffh" at the column address 2048 start set block address = 0 check "ffh" increment block address last block ? end no yes yes create (or update) no initial of the 1st and 2nd page in the block invalid block(s) table www..net
- 15 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 3.3 error in write or read operation within its life time, additional invalid blocks may develop with nand flash memory. refer to the qualification report for the a ctual data.the following possible failure modes should be considered to implement a highly reliable system. in the case of status read failure after era se or program, block replacement should be done. because program st atus fail during a page program does not affect the data of the other pages in th e same block, block replacement can be executed with a page-siz ed buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. in case of read, ecc must be employed. to improve the efficiency of memory space, it is recommended that the read or verifica- tion failure due to single bit error be reclaimed by ecc without any block replacement. the said additional block failure rate does not include those reclaimed blocks. ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection program flow chart failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read single bit failure verify ecc -> ecc correction start i/o 6 = 1 ? i/o 0 = 0 ? no * write 80h write address write data write 10h read status register program completed or r/b = 1 ? program error yes no yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * www..net
- 16 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d nand flash technical notes (continued) * step1 when an error happens in the nth page of the bloc k ?a? during erase or program operation. * step2 copy the data in the 1st ~ (n-1)th page to the same location of another free block. (block ?b?) * step3 then, copy the nth page data of the block ?a? in the buffer memory to the nth page of the block ?b?. * step4 do not erase or program to block ?a? by creating an ?invalid block? table or other appropriate scheme. erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes write 30h block replacement buffer memory of the controller. 1st block a block b (n-1)th nth (page) { 1st (n-1)th nth (page) { an error occurs. 1 2 www..net
- 17 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 3.4 addressing for program operation within a block, the pages must be programm ed consecutively from the lsb (least signific ant bit) page of the block to msb (most significant bit) pages of the block. random page address programming is prohibited. in th is case, the definition of lsb page is the lsb among the pages t o be programmed. therefore, lsb doesn?t need to be page 0. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 : : : : www..net
- 18 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 3.5 system interface using ce dont-care. for an easier system interface, ce may be inactive during the data-loading or serial access as shown below. the internal 8,628byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. in addition, for voice or audio appli cations which use slow cycle time in the order of -seconds, de-activating ce during the data-loading and serial access would provide significant savings in power consumption. program operation with ce don?t-care read operation with ce don?t-care ce we t wp t ch t cs address(5cycles) 80h data input ce cle ale we data input ce don?t-care 10h t cea out t rea ce re i/o 0 ~ 7 i/ox address(5cycle) 00h ce cle ale we data output(serial access) ce don?t-care r/b t r re 30h i/ox www..net
- 19 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.0 timing diagrams 4.1 command latch cycle 4.2 address latch cycle ce we cle ale command t cls t cs t clh t ch t wp t als t alh t ds t dh i/ox ce we cle ale col. add1 t cs t wc t wp t als t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t wc t wp t ds t dh t alh t als t wh t ds t dh t wp i/ox col. add2 row add1 row add2 t wc t wh t alh t als t ds t dh row add3 t alh t cls www..net
- 20 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.3 input data latch cycle 4.4 * serial access cycle after read (cle=l, we =h, ale=l) note : 1 ) transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2) trloh is valid when frequency is higher than 20mhz. trhoh starts to be valid when frequency is lower than 20mhz. ce cle we din 0 din 1 din final ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp i/ox re ce r/b dout dout dout t rc t rea t rr t rhoh t rea t reh t rea t rhz i/ox t chz t rhz www..net
- 21 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.5 serial access cycle after read (edo type, cle=l, we =h, ale=l) note : 1) transition is measured at 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 2) trloh is valid when frequency is higher than 20mhz. trhoh starts to be valid when frequency is lower than 20mhz. 4.6 status read cycle re ce r/b i/ox t rr t cea t rea t rp t reh t rc t rhz t chz t rhoh t rloh dout dout t rea ce we cle re 70h/f1h status output t clr t clh t wp t ch t ds t dh t rea t ir t rhoh t whr t cea t cls i/ox t chz t rhz t cs www..net
- 22 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.7 read operation 4.8 read operation (intercepted by ce ) ce cle r/b we ale re busy 00h col. add1 col. add2 row add1 dout n dout n+1 column address row address t wb t ar t r t rc t rhz t rr dout m t wc row add2 30h t clr i/ox row add3 ce cle r/b we ale re busy 00h dout n dout n+1 dout n+2 row address column address t wb t ar t chz t r t rr t rc 30h i/ox col. add1 col. add2 row add1 row add2 row add3 t clr t csd www..net
- 23 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.9 random data output in a page ce cle r/b we ale re busy 00h dout n dout n+1 row address column address t w b t ar t r t rr t r c 30h 05h column address dout m dout m+1 i/ox col. add1 col. add2 row add1 row add2 col add1 col add2 row add3 e0h t rhw t clr t whr t rea www..net
- 24 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.10 page program operation note : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serialdata input command column address row address 1 up to m byte serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc i/ox co.l add1 col. add2 row add1 row add2 row add3 t adl t whr www..net
- 25 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.11 page program operati on with random data input ce cle r/b we ale re 80h 70h i/o 0 din n din 10h m serial data input command column address row address serial input program command read status command t prog t wb t wc t wc 85h random data input command column address t wc din j din k serial input i/ox col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add3 t adl t adl t whr i/o 0 =0 successful program i/o 0 =1 error in program note : 1) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. www..net
- 26 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.12 copy-back program operation 00h i/o x 85h column address row address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc busy t wb t r busy 10h copy-back data input command 35h column address row address data 1 data n col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add1 row add2 row add3 row add3 70h t adl t whr data 1 data n t rc ce cle r/b we ale re i/ox note : 1) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. www..net
- 27 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.13 copy-back program operat ion with random data input 00h i/o x 85h column address row address read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc busy t wb t r busy 10h copy-back data input command 35h column address row address data 1 data n col. add1 col. add2 row add1 row add2 col. add1 col. add2 row add1 row add2 row add3 row add3 70h t adl t whr data 1 data n t rc ce cle r/b we ale re i/ox note : 1) tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. www..net
- 28 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.14 two-plane page program operation 80h i/o 0 ~ 7 r/b 11h ex.) two-plane page program t dbsy address & data input 81h 10h address & data input 70h/f1h t prog col add1,2 & row add 1,2,3 8,628 byte data ce cle r/b we ale re 80h din n din 11h m serial data input command column address program tdbsy twb twc command (dummy) din n 10h i/o program confirm command (true) 81h 70h/f1h page row address i/ox 1 up to 8,628 byte data serial input din m read status command t dbsy : typ. 500ns max. 1 s col add1 col add2 row add1 row add2 row add3 col add1 col add2 row add1 row add2 row add3 col add1,2 & row add 1,2,3 8,628 byte data note : any command between 11h and 81h is prohibited except 70h/f1h and ffh. note twhr i/o 0 =1 error in program i/o 0 =0 successful program twb tprog www..net
- 29 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.15 block erase operation ce cle r/b we ale re 60h erase command read status command i/o 0 =1 error in erase d0h 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase row address t wc auto block erase setup command i/ox row add1 row add2 row add3 t whr www..net
- 30 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.16 two-plane block erase operation block erase setup command1 erase confirm command read status command 60h row add1,2,3 i/o 0 ~ 7 r/b 60h a 9 ~ a 25 d0h t bers ex.) address restriction for two-plane block erase operation ce cle r/b i/o x we ale re 60h row add1 d0h 70h/f1h i/o 0 busy t wb t bers t wc d0h 70h/f1h address address row add1,2,3 i/o 0 = 0 successful erase i/o 0 = 1 error in erase row add2 row add3 60h row add1 d0h row add2 row add3 row address t wc block erase setup command2 row address t whr www..net
- 31 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 4.17 read id operation note : 1) when reading the 6th cycle of read id, may acquire the "ech" vlalue device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle K9F4G08U0D dch 10h 95h 54h k9k8g08u0d d3h 11h 58h k9k8g08u1d dch 10h 54h k9wag08u1d d3h 11h 58h ce cle we ale re 90h read id command maker code device code 00h ech t rea address 1cycle i/ox t ar device 4th cyc. code 3rd cyc. 5th cyc. 6th cyc. www..net
- 32 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 3rd id data 4th id data 5th id data description 1 st byte 2 nd byte 3 rd byte 4 th byte 5 th byte maker code device code internal chip number, cell type, number of simultaneously programmed pages, etc page size, block size,redundant area size, organization, serial access minimum plane number, plane size description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 page size (w/o redundant area ) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 block size (w/o redundant area ) 64kb 128kb 256kb 512kb 0 0 0 1 1 0 1 1 redundant area size ( byte/512byte) 8 16 0 1 organization x8 x16 0 1 serial access minimum 50ns/30ns 25ns reserved reserved 0 1 0 1 0 1 0 1 description i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 plane number 1 2 4 8 0 0 0 1 1 0 1 1 plane size (w/o redundant area) 64mb 128mb 256mb 512mb 1gb 2gb 4gb 8gb 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 reserved 0 0 0 www..net
- 33 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 5.0 device operation [figure 4] read operation 5.1 page read page read is initiated by writing 00h-30h to the command register along with five address cycles. after initial power up, 00h c ommand is latched. there- fore only five address cycles and 30h command initiates that operation after initial power up. the 2,112 bytes of data within the selected page are trans- ferred to the data registers in less than 25 p s(t r ). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the data starting from the selected column address up to the last column address. the device may output random data in a page instead of the cons ecutive sequential data by writing random data output command. t he column address of next data, which is going to be out, may be changed to the addr ess which follows random data output command. random data out put can be operated multiple times regardless of how many times it is done in a page. address(5cycle) 00h col. add.1,2 & row add.1,2,3 data output(serial access) data field spare field ce cle ale r/b we re t r 30h i/ox | | | | | | www..net
[figure 5] random data output in a page [figure 6] program & read status operation - 34 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 5.2 page program the device is programmed bas ically on a page basis, but it does allow multiple partial page programming of a word or consecutiv e bytes up to 2,112, in a single page program cycle. the number of consecutive partial pa ge programming operation within the same page without an interve ning erase operation must not exceed 4 times for a single page. the addressing shoul d be done in sequential order in a block. a page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded in to the data register, followed by a non-volatile programming p eriod where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input command(80h) , followed by the fi ve cycle address input s and then serial data loading. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). random da ta input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command(10h) initiates the programming process. writing 10h alone without previously entering t he serial data will not initiate the progr amming process. the internal write sta te controller automatically exe- cutes the algorithms and timings necessary fo r program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status register command may be entered to read the stat us register. the system controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while progra m- ming is in progress. when the page program is complete, the writ e status bit(i/o 0) may be checked(figure 6). the internal writ e verify detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status command mode until an other valid command is written to the command register. address 00h data output r/b re t r 30h address 05h e0h 5cycles 2cycles data output data field spare field data field spare field i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 80h r/b address & data input i/o0 pass data 10h 70h fail t prog i/ox col. add.1,2 & row add.1,2,3 "0" "1" www..net
[figure 7] random data input in a page [figure 9] page copy-back program operation with random data input [figure 8] page copy-back program operation - 35 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 5.3 copy-back program copy-back program with read for copy-back is cond to quickly and efficiently rewrite data stored in one page without data re-lo ading when the bit error is not in data stored. since the time-cons uming re-loading cycles are removed, the system performance is improved. the benefit is especially obvious when a portion of a block is updated and the rest of the block al so needs to be copied to the newly assigned free block. copy-b ack operation is a sequen- tial execution of read for copy-back and of copy-back program with the destination page address. a read operation with "35h" co mmand and the address of the source page moves the whole 2,112-byte data into the internal data buffer. a bit error is checked by sequential reading the data output. in the case where there is no bit error, the data do not need to be reloaded. therefore copy-back pr ogram operation is initiated b y issuing page-copy data- input command (85h) with destination page address. actual progra mming operation begins after program confirm command (10h) is i ssued. once the program process starts, the read status register command (70h) may be entered to read the status register. the system controlle r can detect the com- pletion of a program cycle by monitoring the r/b output, or the status bit(i/o 6) of the status r egister. when the copy-back program is complete, the write status bit(i/o 0) may be checked(figure 8 & figure 9). the command register remains in read status command mode until another valid com- mand is written to the command register. during copy-back program, data modificati on is possible using random data input command (85h) as shown in figure 9. 80h r/b address & data input i/o0 pass 10h 70h fail t prog 85h address & data input i/ox col. add.1,2 & row add1,2,3 col. add.1,2 data data "0" "1" "0" "1" 00h r/b add.(5cycles) i/o0 pass fail t prog t r source address destination address i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 35h data output 85h add.(5cycles) 10h 70h | | r/b source address destination address there is no limitation for the number of repetition. i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 & row add.1,2,3 col. add.1,2 00h add.(5cycles) 35h t r data output 85h add.(5cycles) data | | 85h add.(2cycles) data 10h t prog 70h www..net
[figure 10] block erase operation [figure 11] two-plane page program - 36 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 5.4 block erase the erase operation is done on a block basis. block address loading is acco mplished in three cycles initiated by an erase setup command(60h). only address a 18 to a 29 is valid while a 12 to a 17 is ignored. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by executi on command ensures that memory contents are not accidentally erased due to external noise conditions. at the rising edge of we after the erase confirm command input, the internal write cont roller handles erase and erase- verify. when the erase operation is completed, the write status bit(i/o 0) ma y be checked. figure 10 details the sequence. 5.5 two-plane page program two-plane page program is an extension of p age program, for a single plane with 2112 by te page registers. since the device is e quipped with two mem- ory planes, activating the two sets of 2112 byte page regi sters enables a simultaneous programming of two pages. after writing the first set of data up to 2112 byte into the selected page register, dummy page program command (11h) instead o f actual page program command (10h) is inputted to finish data-loading of the fi rst plane. since no programming process is involved, r/b remains in busy state for a short period of time(tdbsy). read status command (70h/f1h) may be issued to fi nd out when the device returns to ready state by polling the r eady/busy status bit(i/ o 6). then the next set of data for the other plane is inpu tted after the 81h command and address sequences. after inputting data for the last plane, actual true page program(10h) instead of dummy page program command (11h) must be followed to start the programming process. the opera tion of r/b and read status is the same as that of page program. althougth two planes are programmed simultaneously , pass/fail is not available for each page when the program operation completes. status bit of i/o 0 is set to "1" when any of the pages fails. restriction in addressing with two-plane page program is shown is figure 11. 60h row add 1,2,3 r/b address input(3cycle) i/o0 pass d0h 70h fail t bers i/ox "0" "1" 80h 11h data input plane 0 (2048 block) block 0 block 2 block 4094 block 4092 80h i/o 0 ~ 7 r/b address & data input 11h 81h 10h t dbsy t prog 70h/f1h address & data input note :1. it is noticeable that same row address except for a 18 is applied to the two blocks 81h 10h plane 1 (2048 block) block 1 block 3 block 4095 block 4093 a 0 ~ a 11 : valid a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? a 0 ~ a 11 : valid a 12 ~ a 17 : valid a 18 : fixed ?high? a 19 ~ a 29 : valid 2. any command between 11h and 81h is prohibited except 70h/f1h and ffh. note* 2 www..net
[figure 12] two-plane block erase operation [figure 13] two-plane copy-back program operation - 37 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 5.6 two-plane block erase basic concept of two-plane block erase operat ion is identical to that of two-plane p age program. up to two blocks, one from eac h plane can be simul- taneously erased. standard block erase comm and sequences (block erase setup command(60h) followed by three address cycles) may be repeated up to twice for erasing up to two blocks. on ly one block should be selected from each plane. the erase confirm command(d0h) initia tes the actual erasing process. the completion is detected by monitoring r/b pin or ready/busy status bit (i/o 6). 5.7 two-plane copy-back program two-plane copy-back program is an extension of copy-back program, for a single plane with 2112 byte page registers. since the d evice is equipped with two memory planes, activating the two sets of 2112 by te page registers enables a simu ltaneous programming of two pages. note : 1) copy-back program operation is allowed only within the same memory plane. 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. 60h i/o x r/b 60h d0h i/o0 pass fail t bers address (3 cycle) address (3 cycle) 70h/f1h "0" "1" a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? a 12 ~ a 17 : fixed ?low? a 18 : fixed ?high? a 19 ~ a 29 : valid 00h r/b add.(5cycles) t r source address on plane0 35h i/ox col. add.1,2 & row add.1,2,3 1 r/b 85h 70h/f1h t prog add.(5cycles) destination address 10h i/ox col. add.1,2 & row add.1,2,3 81h add.(5cycles) destination address col. add.1,2 & row add.1,2,3 11h t dbsy a 0 ~ a 11 : fixed ?low? a 12 ~ a 17 : valid a 18 : fixed ?high? a 19 ~ a 29 : valid 1 note2 a 0 ~ a 11 : fixed ?low? a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? data field spare field data field spare field (1) (2) (3) (3) plane0 plane1 source page target page source page target page (1) : read for copy back on plane0 (2) : read for copy back on plane1 (3) : two-plane copy-back program 00h add.(5cycles) source address on plane1 35h col. add.1,2 & row add.1,2,3 t r data output data output | | | | www..net
[figure 14] two-plane copy-back program operation with random data input - 38 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d note: 1) copy-back program operation is allowed only within the same memory plane. 2) any command between 11h and 81h is prohibited except 70h/f1h and ffh. r/b 85h 11h t dbsy add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 00h r/b add.(5cycles) t r source address on plane0 35h i/ox col. add.1,2 & row add.1,2,3 1 r/b 81h 10h t prog add.(5cycles) data 85h data i/ox col. add.1,2 & row add.1,2,3 col. add.1,2 add.(2cycles) 1 2 2 destination address a 0 ~ a 11 : valid a 12 ~ a 17 : fixed ?low? a 18 : fixed ?low? a 19 ~ a 29 : fixed ?low? destination address a 0 ~ a 11 : valid a 12 ~ a 17 : valid a 18 : fixed ?high? a 19 ~ a 29 : valid note2 00h add.(5cycles) source address on plane1 35h col. add.1,2 & row add.1,2,3 t r data output data output | | | | www..net
- 39 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 5.8 read status the device contains a status register whic h may be read to find out whether program or erase operation is completed, and whethe r the program or erase operation is completed successfully. after writing 70h/f1h comm and to the command register, a read cycle outputs the content of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows t he system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific sta- tus register definitions and table 3 for spec ific f1h status register definitions. the command register remains in status read mode until further com- mands are issued to it. therefore, if the status register is read during a random r ead cycle, the read command(00h) should be g iven before starting read cycles. [table 2] status register definition for 70h command note : 1) i/os defined ?not use? are recommended to be masked out when read st atus is being executed. [table 3] status register definition for f1h command note : 1) i/os defined ?not use? are recommended to be masked out when read st atus is being executed. i/o page program block erase read definition i/o 0 pass/fail pass/fail not use pass : "0" fail : "1" i/o 1 not use not use not use don?t -cared i/o 2 not use not use not use don?t -cared i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy busy : "0" ready : "1" i/o 7 write protect write protect write protect protected : "0" not protected : "1" i/o no. page program block erase read definition i/o 0 chip pass/fail chip pass/fail not use pass : "0" fail : "1" i/o 1 plane0 pass/fail plane0 pass/fail not use pass : "0" fail : "1" i/o 2 plane1 pass/fail plane1 pass/fail not use pass : "0" fail : "1" i/o 3 not use not use not use don?t -cared i/o 4 not use not use not use don?t -cared i/o 5 not use not use not use don?t -cared i/o 6 ready/busy ready/busy ready/busy b usy : "0" ready : "1" i/o 7 write protect write protect write protect protected : "0" not protected : "1" "1"otected www..net
[figure 15] read id operation [figure 16] reset operation - 40 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 5.9 read id the device contains a product identificati on mode, initiated by writing 90h to the command register, followed by an address inp ut of 00h. five read cycles sequentially output the manufacturer code(ech), and the device code and 3rd, 4th, 5th cycle id respectively. the command regis ter remains in read id mode until further commands are issued to it. figure 15 shows the operation sequence. note : 1) when reading the 6th cycle of read id, may acquire the "ech" vlalue 5.10 reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during ran dom read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait fo r the next command, and the status register is cleared to value c0h when wp is high. if the device is already in reset state a new reset command will be accepted by the command register. the r/b pin changes to low for trst after the reset command is written. refer to figure 16 below. [table 4] device status device device code (2nd cycle) 3rd cycle 4th cycle 5th cycle K9F4G08U0D dch 10h 95h 54h k9k8g08u0d d3h 11h 58h k9k8g08u1d dch 10h 54h k9wag08u1d d3h 11h 58h after power-up after reset operation mode mode 00h command is latched waiting for next command ce cle i/o x ale re we 90h 00h address. 1cycle maker code device code t cea t ar t rea t whr t clr device 4th cyc. code ech 3rd cyc. 5th cyc. ffh i/o x r/b t rst www..net
[figure 17] rp vs tr ,tf & rp vs ibusy - 41 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 5.11 ready/ busy the device has a r/b output that provides a hardware method of indicating the comp letion of a page program, erase and random read completion. the r / b pin is normally high but transit ions to low after program or erase command is written to the command register or random read i s started after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby al lowing two or more r/b outputs to be or-tied. because pull-up resi stor value is related to tr(r/b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the fol- lowing reference chart(figure 17). its val ue can be determined by the following guidance. v cc r/b open drain output device gnd rp ibusy busy ready vcc voh tf tr vol 3.3v device - v ol : 0.4v, v oh : 2.4v c l tr,tf [s] ibusy [a] where i l is the sum of the input currents of all devices tied to the r/b pin. rp value guidance rp(max) is determined by maximum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + 6 i l = 3.2v 8ma + 6 i l rp(ohm) ibusy tr @ vcc = 3.3v, ta = 25 q c , c l = 50pf 1k 2k 3k 4k 100n 200n 2m 1m 50 tf 100 150 200 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 tr,tf [s] ibusy [a] rp(ohm) ibusy tr @ vcc = 2.7v, ta = 25 q c , c l = 30pf 1k 2k 3k 4k 100n 200n 2m 1m 30 tf 60 90 120 2.3 2.3 2.3 2.3 2.3 1.1 0.75 0.55 www..net
[figure 18] ac waveforms for power transition - 42 - datasheet k9k8g08u0d flash memory rev. 0.2 advance K9F4G08U0D k9k8g08u1d k9wag08u1d 5.12 data protection & power up sequence the device is designed to offer pr otection from any involuntary program/erase du ring power-transitions. an internal voltage det ector disables all functions whenever vcc is below about 2v(3.3v device). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power- down. a recovery time of minimum 100 p s is required before internal circuit gets ready for any command sequences as shown in figure 18. the two step command sequence for program/erase prov ides additional software protection. note : during the initialization, the device consumes a maximum current of 30ma (icc1) v cc wp high | | we | | | ready/busy 5 ms max operation 100 p s ~ 2.3v ~ 2.3v invalid don?t care don?t care www..net

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